1. Field of the Invention
The present invention relates generally to multiple processor systems, and more particularly to a technique for accelerating data transfers from a memory storage unit to a device in a multiple processor system.
2. Related Art
In multiple processor systems, devices, such as microprocessors, memory banks, and peripheral control units, are interconnected via a plurality of buses. Such systems employ rules for allocating machine resources, such as memory or data buses, known as arbitration. In multiple processor bus environments, where multiple devices are competing for bus access for data transfer, each device must arbitrate to obtain ownership of the bus. For example, when a processor requests a unit of data from memory, some time later that data is delivered to the processor. Once the memory unit receives the request for data, the memory unit must read the data location, access the physical data, and deliver the data to the processor. Memory latency between when a request for data is received and when the data is transmitted can be time consuming.
Before the data can be delivered to the processor from the memory (or cache), the bus agent delivering the data must arbitrate to gain ownership of the data bus. Arbitration can be time consuming. In a directory based system where the memory controller stores the directory information in the same medium as the data itself the memory controller will obtain the directory information at the same instant it obtains the associated data for transfer to a requesting processor. If the directory state is not proper then the data which is read is not forwarded and action is taken to put the directory in the proper state to satisfy the request. The majority of the time however the data is able to be forwarded to the processor. If the memory controller waited until it observed the directory information before beginning arbitration it would waste the time of arbitration in satisfying the request. If the memory controller had direct control of arbitration it could begin arbitration to have the data bus available when the data was available from it's storage medium and either deliver the data on the bus without losing the time of arbitration or release the bus without data transfer if the directory state is not proper. In large multiprocessor systems the memory controller becomes separated from the processor bus by intervening busses such that a method and system are needed to speculatively arbitrate the processor bus for data delivery.